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Auvra

10 — Roadmap & Risks

Status authority · reconciled 2026-08-30. This file is the single source for project-wide milestone status and immediate priorities. Subsystem documents define architecture and acceptance criteria; Git history records implementation chronology.

1. Phased plan: software and bench prototype

Section titled “1. Phased plan: software and bench prototype”

P0–P6 describe the existing N100/USB/HDMI/S90 bench route. They do not qualify the Tang card or a production instrument. The selected integrated hardware path has separate F0–F10 gates below.

flowchart LR
    P0["P0 · Bench bring-up<br/>N100 + RT Linux + USB audio<br/>measure cyclictest / RTL"]
    P1["P1 · Sound on keys<br/>RP2350 keybed scanner → USB-MIDI<br/>into a synth engine"]
    P2["P2 · Control surface<br/>RP2350 nodes on I²C via MCP2221A<br/>knobs/buttons/LEDs"]
    P3["P3 · UI & silent boot<br/>touch kiosk, no boot visible"]
    P4["P4 · Motor-faders<br/>position recall + touch"]
    P5["P5 · Integration<br/>fit into S90, power tree, thermals"]
    P6["P6 · Platform image<br/>Yocto image, OTA, polish"]
    P0 --> P1 --> P2 --> P3 --> P4 --> P5 --> P6

Milestones & exit criteria

Section titled “Milestones & exit criteria”
Phase Goal Done when…
P0 RT platform proven cyclictest Max < 30 µs under load; cpal -> ALSA stable at 64–128 frames, no xruns/hour.1
P1 Keys make sound RP2350 scans the S90 matrix, velocity calibrated, plays a synth via USB-MIDI < 6 ms key→sound.
P2 Controls work ≥ 1 RP2350 node on I²C through MCP2221A; host maps pots/buttons/LEDs reliably at ~1 kHz.
P3 It’s an appliance Power-on shows no boot output; kiosk UI up; touch maps correctly.
P4 Faders Motor-faders recall positions; touch-grab pauses the motor.
P5 In the box Everything mounted in the S90; single 19 V inlet; thermals verified; clean audio noise floor.
P6 Bench platform reproducible Immutable Yocto image, A/B OTA, documented build; integrated hardware still needs F0–F10.

Decision point after P5: stay on x86/N100 or migrate to ARM (02) — decide on measured DSP headroom at target voice count.

Software track (parallel)

Section titled “Software track (parallel)”

The software milestones are defined in 12-plugin-host-and-patches.md §8:

Milestone Outcome Status
M1 Platform-free engine and plugin traits Done
M2 Lock-free mixer, limiter, telemetry and disposal Done
M3 Real CLAP instruments/effects and parameter introspection Done
M4 Slots, zones, layers/splits and semantic musical-event routing Done
M5 Patch/setlist persistence, async CLAP ownership and tail-safe switching Done
M6 Control IPC, abstract hardware mapping and target/QEMU integration Active

The MIDI-2-capable internal event contract is complete; MIDI 1 is adapted at the platform edge. Native UMP I/O, MIDI-CI and host play aids are later work and do not block M6 (05 §3).

Immediate priority: M6 control loop

Section titled “Immediate priority: M6 control loop”

M6 closes both directions of the product control path:

  1. Done (M6.1): versioned auvra-ctld ↔ app IPC in auvra-proto, with physical input/status events, LED/fader feedback, reconnect and QEMU probe;
  2. Next (M6.2): platform-free control targets, hardware profiles, paging and soft takeover;
  3. scriptable RP2350 simulation;
  4. automated simulator → QEMU/MCP2221 → I²C → ctld → app → engine verification, including LED and motor-fader feedback;
  5. the same stack measured on the N100/PREEMPT_RT target.

Selected FPGA integration track (parallel to software MVP)

Section titled “Selected FPGA integration track (parallel to software MVP)”

The Tang Mega 138K Pro is the selected development platform for integrated PCIe/ALSA sound, FPGA framebuffer scanout/touch, and keybed/control I/O. Its documented interfaces establish feasibility, not a tested Auvra card. The F0–F10 gates in 17-fpga-audio-interface.md cover PCIe/DMA, 2-in/4-out I²S conversion, display/touch, S90 matrix scanning, and integrated fault/latency qualification. F7 AES67 networking is parallel and does not block local instrument I/O. Until F10, external USB audio, N100 HDMI, USB-MIDI and MCP2221A remain the software MVP/bench fallback. F1 compares Gowin SGDMA and LitePCIe as the single DMA substrate for an Auvra-owned PCIe ABI; Corundum remains a queue/PTP/test reference, not the default port.

2. Risk register

Section titled “2. Risk register”
# Risk Likelihood Impact Mitigation
R1 S90 keybed pinout/protocol differs from assumptions Medium High Measure the real ribbon early (P1); template from floretan/p150; budget time to reverse-engineer.2
R2 RT latency on fanless N100 not stable at low buffers Low–Med High Proven achievable (< 20 µs jitter) but verify per board; fall back to 128 frames (~5.3 ms).1
R3 SMIs/firmware add hidden latency spikes Medium Med hwlatdetect; disable BIOS features; lock CPU freq (03).3
R4 I²C bus unreliable across chassis (capacitance/noise) Medium Med Short bus, correct pull-ups, bus buffer, scope-verify; keep notes on USB-MIDI not I²C (06).4
R5 FPGA/ALSA or converter RTL worse than target Medium High Keep class-compliant RME as comparator/fallback; measure 2-in/4-out analog RTL and xruns before replacing it (17 F5).5
R6 Fanless thermals throttle under sustained DSP Medium Med Vents/quiet fan; monitor temps in P5; cap voice count.
R7 Motor-fader inrush stresses 5 V rail Low Med Size buck/fuse for stall current; local decoupling (08).
R8 RP2350 early-silicon GPIO errata Low Low Use A3/A4 stepping.6
R9 Scope creep (engine + UI are large) High Med Plugin-host architecture fixed in 12; plugin DSP internals stay out of scope; phase strictly.
R10 ARM migration costlier than hoped Med Med Keep Rust engine platform-free and Linux audio behind ALSA/cpal; retarget Yocto recipes and PCIe driver only after measured need (02).
R11 A misbehaving in-process plugin stalls the RT thread Medium High Curated signed store; watchdog + <1 s session restore; quarantine repeat offenders; sandbox path kept open (12 §6).
R12 CLAP catalog/params too thin for a GUI-less instrument Medium Med Param-first hosting and remote-controls verified against Surge XT; spot-check Dexed/Odin2 and retain generated parameter lists as fallback (12 §9).
R13 Custom PCIe DMA/ALSA/network path is unstable or costs more latency than expected Medium High Select Gowin SGDMA or LitePCIe through identical F1 measurements, keep one versioned Auvra ABI, then use protocol self-tests, fault injection, a 24-hour xrun test, and measured comparison with the external interface (17).
R14 Ethernet MAC lacks the timestamping needed for AES67-grade PTP High High Build timestamp capture at the MAC user boundary; gate network audio on measured PHC/PTP accuracy and interoperability (17).
R15 Gowin tool/IP licence does not permit the intended CI or product distribution Medium High Review the EDA licence and each selected IP EULA before committing to implementation or shipment; keep vendor-generated artifacts isolated (17).
R16 A full Corundum port consumes schedule, FPGA resources, or kernel-maintenance budget without benefiting the audio workload Medium High Do not port it by default; reuse architecture and tests selectively. Reconsider only against measured near-wire-rate general-purpose NIC requirements and compare synthesis/timing against the focused Auvra path (17 §4.1).
R17 Three simultaneous FPGA netdevs starve audio DMA or destabilise the shared PHC Medium High Separate queues/interrupts, strict audio/PTP arbitration priority, one shared PHC, staged RJ45/SFP+/three-port F7 tests, and network-saturation tests while ALSA and RTL AES67 are active (17).
R18 Display refresh or touch/control traffic starves PCIe audio Medium High Prioritize audio DMA, isolate video/control queues and reset domains, and stress F8/F9 with continuous redraw and input while measuring xruns (17).
R19 S90 keys or panel controls are incorrectly assumed to speak I²C High High Measure ribbons and logic levels; scan the passive key matrix via protected GPIO or a scanner MCU. Reserve I²C for verified I²C devices (05, 06).
R20 Sure ADC/DAC modules or analog panel front end fail clock, level, noise or dual-connector requirements Medium High Test one PCM1822 and two PCM5122 boards on a shared clock; separately design/protect balanced XLR and unbalanced jack line I/O (04).
R21 Integrated power tree copied from 19 V bench supply despite Tang 12 V input Medium High Measure all rails and peaks; design separate protected 12 V FPGA rail and analog supplies before common-inlet selection (08).

3. Consolidated open questions ([verify])

Section titled “3. Consolidated open questions ([verify])”

From across the subsystem docs:

  1. Keybed: exact S90 ribbon pinout, matrix size, contacts-per-key, 3.3 V strobe tolerances (05).
  2. RT: per-board cyclictest results; whether disabling BIOS C-states helps or hurts on this board (03).
  3. Audio: measured Linux RTL of the chosen interface at 48 kHz (04).
  4. I²C: max reliable node count / bus length in the actual harness (06).
  5. Display: backlight sysfs name and dimmability; HDMI EDID/mode quirks (07).
  6. Power/mech: S90 internal volume vs Mini-ITX; fader inrush; fanless thermal margin (08).
  7. Integrated FPGA: board/device revision and IP rights; SGDMA versus LitePCIe; 2-in/4-out shared-clock converter RTL/noise; panel and touch routing, framebuffer/DRM/X11 compatibility; S90 key and control pinouts; 12 V power budget and arbitration under full audio/display/control load. Three-port Linux networking and PTP remain separate F7 measurements (17).

4. Explicitly out of scope (separate design efforts)

Section titled “4. Explicitly out of scope (separate design efforts)”
  • The DSP internals of individual plugins (oscillators, filters, voice allocation live inside plugins — the host architecture is fixed in 12).
  • Schematics & PCB layout for the RP2350 node boards and harness.
  • The store service (packaging/signing concept: 12 §7).

Footnotes

Section titled “Footnotes”

  1. LinuxCNC forum, “Intel N100” latency thread. https://forum.linuxcnc.org/18-computer/50817-intel-n100 ↩ ↩2

  2. floretan/p150 keybed scanner. https://github.com/floretan/p150 ↩

  3. Linux Foundation, “SMI latency” debugging. https://wiki.linuxfoundation.org/realtime/documentation/howto/debugging/smi-latency/start ↩

  4. “I²C design mathematics.” https://www.allaboutcircuits.com/technical-articles/i2c-design-mathematics-capacitance-and-resistance/ ↩

  5. RME, “Babyface Pro FS.” https://rme-audio.de/babyface-pro-fs.html ↩

  6. Raspberry Pi, “RP2350 datasheet.” https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf ↩